As is known in the art, for high power Coplanar Waveguide (CPW) MMICs, such as AlGaN/GaN high power amplifiers (HPAs), heat removal is critical for circuit performance and reliability. Current heat sinking methods for GaN MMICs include bonding the back side of the MMIC (the side opposing to the active layer containing active device and transmission lines) to a heat spreader/sink using a thermally conductive epoxy or bonding layer.
As is known in the art, there are two types of thermally conductive epoxies: electrically insulating epoxies (electrically insulating, electrically non-conductive or poorly-conductive epoxies, hereinafter referred to as electrically non-conductive epoxies), are filled with electrically non-conductive materials, with electrical conductivity typically less than 1 Siemens per meter, such as, for example, Aluminum Nitride (AlN) or Alumina (Al2O3) particles; and electrically conductive epoxies, such as epoxies filled with electrically conductive particles, with electrical conductivity higher than 103 Siemens (or mhos) per meter, typically on the order of 107 Siemens per meter, such as Silver (Ag) flakes. Electrically conductive epoxies, can provide >5-fold reduction in Thermal Interface Material (TIM) resistance compared with electrically non-conductive epoxies because of their high thermal conductivity filler, increased percolation afforded by filler geometry and/or improved rheology and viscosity leading to thinner bond-lines, compared to electrically non-conductive epoxies. See R. Prasher, “Thermal Interface Materials: Historical Perspective, Status and Future Directions,” Proceedings of the IEEE, Vol 94. No. 8. 2006. Even when compared to electrically non-conductive epoxies filled with high thermal conductivity fillers such as boron nitride (BN) and diamond, electrically conductive epoxies provide a lower TIM resistance than electrically non-conductive epoxies.
Ideally, an electrically conductive bond layer would be employed for the attachment of the MMIC to the heat sink in order to further minimize the TIM resistance. However, the inventors have recognized that a blanket application of an electrically conductive layer provides a continuous electrically conductive plane under the layer containing active device and transmission lines, and as a result, unwanted Parallel Plate or Waveguide moding can be supported between this plane and the front-side metallization of the CPW MMIC. These modes often interfere with circuit operation and can therefore render the circuit completely nonoperational. Moding provides feedback that can enable unwanted RF oscillations. Even if stable, moding can affect matching circuits, particularly for higher-order harmonic tuning. A method for mode suppression by partial removal of electrically conductive back plane and heat sink is described in U.S. Patent Application Publication No 2012/0063097, inventors Reza et al, assigned to the same assignee as the present invention.
In accordance with the present disclosure, a monolithic microwave integrated circuit structure is provided having: a semiconductor substrate structure having a plurality of active devices and microwave transmission lines having an input section, an output section and a interconnecting section electrically interconnecting the active devices on one surface of the substrate; a thermally conductive, electrically insulating heat sink; and a thermally conductive bonding layer for bonding the heat sink to the substrate, the thermally conductive bonding layer having an electrically conductive portion and a electrically insulating portion, the electrically conductive portion being disposed between the heat sink and an opposite surface of a portion of the substrate having the active devices and the electrically non-conductive portion being disposed on the opposite surface portion overlaying portion of the microwave transmission line section.
In one embodiment, the electrically non-conductive portion overlays a portion of the at least one of the input section and the output section.
In one embodiment, the electrically non-conductive portion overlays at least a portion of the interconnecting section.
In one embodiment, the electrically non-conductive portion overlays at least a middle region of the chip, the middle region being a portion of the microwave transmission line section between the input section and the output section.
In one embodiment, the electrically non-conductive portion overlays a plurality of different portions of the microwave transmission line section.
In one embodiment, the electrically conductive portion has an electrical conductivity more than 1000 times greater than the electrical conductivity of the electrically non-conductive portion.
With such an arrangement, co-curing selectively patterned electrically conductive and electrically non-conductive epoxies achieves low thermal resistance die attach while simultaneously suppressing parallel-plate moding that would otherwise be detrimental to MMIC operation. This is achieved by positioning the electrically conductive epoxy in locations where it enhances thermal management of high dissipation regions of the MMIC (e.g., beneath FETs) while simultaneously positioning electrically non-conductive epoxy in locations beneath the microwave transmission line section to prevent Parallel Plate moding.
The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.
Like reference symbols in the various drawings indicate like elements.